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| TC7126/A 3-1/2 Digit Analog-to-Digital Converters Features * Internal Reference with Low Temperature Drift - TC7126: 80ppm/C Typical - TC7126A: 35ppm/C Typical * Zero Reading with Zero Input * Low Noise: 15VP-P * High Resolution: 0.05% * Low Input Leakage Current: 1pA Typ., 10pA Max. * Precision Null Detectors with True Polarity at Zero * High-Impedance Differential Input * Convenient 9V Battery Operation with Low Power Dissipation: 500W Typ., 900W Max. General Description The TC7126A is a 3-1/2 digit CMOS analog-to-digital converter (ADC) containing all the active components necessary to construct a 0.05% resolution measurement system. Seven-segment decoders, digit and polarity drivers, voltage reference, and clock circuit are integrated on-chip. The TC7126A directly drives a liquid crystal display (LCD), and includes a backplane driver. A low cost, high resolution indicating meter requires only a display, four resistors, and four capacitors. The TC7126A's extremely low power drain and 9V battery operation make it ideal for portable applications. The TC7126A reduces linearity error to less than 1 count. Rollover error (the difference in readings for equal magnitude, but opposite polarity input signals) is below 1 count. High-impedance differential inputs offer 1pA leakage current and a 1012 input impedance. The 15VP-P noise performance ensures a "rock solid" reading, and the auto-zero cycle ensures a zero display reading with a 0V input. The TC7126A features a precision, low drift internal voltage reference and is functionally identical to the TC7126. A low drift external reference is not normally required with the TC7126A. Applications * Thermometry * Bridge Readouts: Strain Gauges, Load Cells, Null Detectors * Digital Meters and Panel Meters: - Voltage/Current/Ohms/Power, pH * Digital Scales, Process Monitors Device Selection Table Package Code CPL IPL CKW CLW Package 40-Pin PDIP 40-Pin PDIP (TC7126 Only) 44-Pin PQFP 44-Pin PLCC Temperature Range 0C to +70C -25C to +85C 0C to +70C 0C to +70C 2002 Microchip Technology Inc. DS21458B-page 1 (c) TC7126/A Package Type 44-Pin PLCC VREF+ VREF+ CREF+ VREFOSC1 OSC2 OSC3 44-Pin PQFP ANALOG COMMON VIN+ CREFVBUFF TEST VIN- VINT CAZ NC V+ C1 D1 A1 B1 6 F1 7 G1 8 E1 9 D2 10 C2 11 NC 12 B2 13 A2 14 F2 15 E2 16 D3 17 5 4 3 2 1 44 43 42 41 40 39 VREF38 CREF+ 37 CREF36 ANALOG COMMON 35 VIN+ 34 NC 33 VIN32 CAZ 31 VBUFF 30 VINT 29 VNC 1 NC 2 TEST 3 OSC3 4 NC 5 OSC2 6 OSC1 7 V+ 8 D1 9 C1 10 B1 11 44 43 42 41 40 39 38 37 36 35 34 33 NC 32 G2 31 C3 30 A3 V29 G3 28 BP 27 POL 26 AB4 25 E3 24 F3 23 B3 TC7126CLW TC7126ACLW TC7126CKW TC7126ACKW 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22 AB4 A1 F1 G1 POL BP E1 D2 G3 C3 NC G2 C2 40-Pin PDIP (Normal) V+ D1 C1 B1 1's A1 F1 G1 E1 D2 1 2 3 4 5 6 7 8 9 44-Pin PDIP (Reverse) OSC1 OSC2 OSC3 TEST 1 2 3 4 Normal Pin Configuration 40 OSC1 39 OSC2 Reverse Pin Configuration 40 V+ 39 D1 38 C1 37 B1 36 A1 35 F1 1's 38 OSC3 37 TEST 36 VREF+ 35 VREF- VREF+ 5 VREFCREF+ CREF6 7 8 C2 10 10's B2 11 A2 12 TC7126CPL TC7126ACPL TC7126IPL TC7126AIPL 34 CREF+ 33 CREF32 ANALOG COMMON 31 VIN+ 30 VIN29 CAZ 28 VBUFF 27 VINT 26 V25 G2 24 C3 23 A3 22 G3 21 BP (Backplane) 100's 100's ANALOG 9 COMMON VIN+ 10 VIN- 11 CAZ 12 TC7126RCPL TC7126ARCPL TC7126RIPL TC7126ARIPL 34 G1 33 E1 32 D2 31 C2 30 B2 29 A2 28 F2 10's F2 13 E2 14 VBUFF 13 VINT 14 V15 27 E2 26 D3 25 B3 24 F3 100's D3 15 100's B3 16 G2 16 C3 A3 17 18 F3 17 E3 18 19 23 E3 22 AB4 1000's 1000's AB4 G3 19 BP 20 (Backplane) POL 20 (Minus Sign) 21 POL (Minus Sign) NC = No Internal Connection (c) DS21458B-page 2 2002 Microchip Technology Inc. D3 B3 A3 B2 A2 F2 E3 E2 F3 TC7126/A Typical Application 0.1F 34 1M + Analog Input - 0.01F 30 VIN32 ANALOG COMMON 28 180k 0.33 F 29 VBUFF VREF+ 36 CAZ VREFVOSC3 OSC1 38 COSC 40 ROSC 50pF 560k To Analog Common (Pin 32) 35 26 1 Conversion/Sec POL BP V+ CREF+ 31 VIN+ 33 CREF2-19 Segment 22-25 Drive 20 21 1 240k + 9V TC7126 TC7126A LCD Minus Sign Backplane 10k 0.15F 27 V INT OSC2 39 Note: Pin numbers refer to 40-pin DIP. 2002 Microchip Technology Inc. DS21458B-page 3 (c) Typical Segment Output V+ 0.5mA Segment Output LCD 2mA (c) DS21458B-page 4 TC7126/A Functional Block Diagram TC7126A RINT VREFCREF- VBUFF V+ 28 1 Integrator - + - ZI DE (+) - DE (-) V+ - 2.8V Clock + Low Temp Co VREF Comparator Thousands BP 21 CAZ CINT VINT 29 27 7-Segment Decode To Digital Section Data Latch 7-Segment Decode 7-Segment Decode / 200 LCD Segment Drivers CREF CREF+ 35 33 VREF+ 34 36 - + AZ ZI & AZ + 10 A ZI & AZ VIN+ 31 Hundreds Tens Units INT DE (-) To Switch Drivers From Comparator Output FOSC 4 Control Logic Internal Digital Ground VTH = 1V 40 OSC1 39 OSC2 ROSC 38 OSC3 COSC 1 6.2V Analog Common 32 DE (+) V+ AZ & DE () 26 V- VINTEST 500 26 V- 2002 Microchip Technology Inc. INT TC7126/A 1.0 ELECTRICAL CHARACTERISTICS *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Supply Voltage (V+ to V-)....................................... 15V Analog Input Voltage (either Input) (Note 1) ... V+ to VReference Input Voltage (either Input) ............ V+ to VClock Input ................................................... Test to V+ Package Power Dissipation (TA 70C) (Note 2): 44-Pin PQFP............................................... 1.00W 40-Pin PLCC ............................................... 1.23W 44-Pin PDIP ................................................ 1.23W Operating Temperature Range: C (Commercial) Devices .................. 0C to +70C I (Industrial) Devices .................... -25C to +85C Storage Temperature Range .............. -65C to +150C TC7126/A ELECTRICAL SPECIFICATIONS Electrical Characteristics: VS = +9V, fCLK - 16kHz, and TA = +25C, unless otherwise noted. Symbol Input ZIR ZRD Zero Input Reading Zero Reading Drift Ratiometric Reading NL Linearity Error -000.0 -- 999 -1 000.0 0.2 999/1000 0.2 +000.0 1 1000 1 Digital Reading V/C Digital Reading Count VIN = 0V Full Scale = 200mV VIN = 0V, 0C TA +70C VIN = VREF, VREF = 100mV Full Scale = 200mV or 2V Max Deviation From Best Fit Straight Line VIN- = VIN+ 200mV VIN = 0V, Full Scale = 200mV VIN = 0V VCM = 1V, VIN = 0V Full Scale = 200mV VIN = 199mV, 0C TA +70C Ext. Ref. Temp Coeff. = 0ppm/C Parameter Min Typ Max Unit Test Conditions Rollover Error eN IL CMRR Noise Input Leakage Current Common Mode Rejection Ratio Scale Factor Temperature Coefficient Analog Common VCTC Analog Common Temperature Coefficient -1 -- -- -- -- 0.2 15 1 50 1 1 -- 10 -- 5 Count VP-P pA V/V ppm/C -- -- -- -- -- -- -- 80 35 35 3.05 -- -- -- 75 100 3.35 -- -- ppm/C ppm/C ppm/C V 250k Between Common and V+ 0C TA +70C ("C" Devices) TC7126 TC7126A -25C TA +85C ("I" Device) (TC7126A) 250k Between Common and V+ VC Note 1: 2: 3: 4: Analog Common Voltage 2.7 Input voltages may exceed the supply voltages, provided the input current is limited to 100A. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Refer to "Differential Input" discussion. Backplane drive is in phase with segment drive for "OFF" segment, 180 out of phase for "ON" segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5: See "Typical Application". 6: During Auto-Zero phase, current is 10-20A higher. A 48kHz ocillator increases current by 8A (Typical). Common current is not included. 2002 Microchip Technology Inc. DS21458B-page 5 (c) TC7126/A TC7126/A ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VS = +9V, fCLK - 16kHz, and TA = +25C, unless otherwise noted. Symbol LCD Drive V SD V BD LCD Segment Drive Voltage LCD Backplane Drive Voltage 4 4 5 5 6 6 VP-P VP-P A V+ to V- = 9V V+ to V- = 9V Parameter Min Typ Max Unit Test Conditions Power Supply IS Note 1: 2: 3: 4: Power Supply Current -- 55 100 VIN = 0V, V+ to V- = 9V (Note 6) Input voltages may exceed the supply voltages, provided the input current is limited to 100A. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Refer to "Differential Input" discussion. Backplane drive is in phase with segment drive for "OFF" segment, 180 out of phase for "ON" segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5: See "Typical Application". 6: During Auto-Zero phase, current is 10-20A higher. A 48kHz ocillator increases current by 8A (Typical). Common current is not included. (c) DS21458B-page 6 2002 Microchip Technology Inc. TC7126/A 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Pin Number (40-Pin PDIP) Normal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PIN FUNCTION TABLE (Reversed) (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21) (20) (19) (18) (17) (16) (15) (14) Symbol V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP G3 A3 C3 G2 VVINT Positive supply voltage. Activates the D section of the units display. Activates the C section of the units display. Activates the B section of the units display. Activates the A section of the units display. Activates the F section of the units display. Activates the G section of the units display. Activates the E section of the units display. Activates the D section of the tens display. Activates the C section of the tens display. Activates the B section of the tens display. Activates the A section of the tens display. Activates the F section of the tens display. Activates the E section of the tens display. Activates the D section of the hundreds display. Activates the B section of the hundreds display. Activates the F section of the hundreds display. Activates the E section of the hundreds display. Activates both halves of the 1 in the thousands display. Activates the negative polarity display. LCD Backplane drive output (TC7106A). Digital Ground (TC7107A). Activates the G section of the hundreds display. Activates the A section of the hundreds display. Activates the C section of the hundreds display. Activates the G section of the tens display. Negative power supply voltage. The integrating capacitor should be selected to give the maximum voltage swing that ensures component tolerance buildup will not allow the integrator output to saturate. When analog common is used as a reference and the conversion rate is 3 readings per second, a 0.047F capacitor may be used. The capacitor must have a low dielectric constant to prevent rollover errors. See Section 6.3, Integrating Capacitor for additional details. Integration resistor connection. Use a 180k resistor for a 200mV full-scale range and a 1.8M resistor for a 2V full scale range. The size of the auto-zero capacitor influences system noise. Use a 0.33F capacitor for 200mV full scale, and a 0.033F capacitor for 2V full scale. See Section 6.1, Auto-Zero Capacitor for additional details. The analog LOW input is connected to this pin. The analog HIGH input signal is connected to this pin. Description 28 29 (13) (12) VBUFF CAZ 30 31 32 (11) (10) (9) VINVIN + ANALOG This pin is primarily used to set the Analog Common mode voltage for battery operaCOMMON tion, or in systems where the input signal is referenced to the power supply. It also acts as a reference voltage source. See Section 7.3, Analog Common for additional details. CREFSee Pin 34. 33 (8) 2002 Microchip Technology Inc. DS21458B-page 7 (c) TC7126/A TABLE 2-1: Pin Number (40-Pin PDIP) Normal 34 PIN FUNCTION TABLE (CONTINUED) (Reversed) (7) Symbol CREF+ Description A 0.1F capacitor is used in most applications. If a large Common mode voltage exists (for example, the VIN - pin is not at analog common) and a 200mV scale is used, a 1F capacitor is recommended and will hold the rollover error to 0.5 count. See Pin 36. The analog input required to generate a full scale output (1999 counts). Place 100mV between Pins 35 and 36 for 199.9mV full scale. Place 1V between Pins 35 and 36 for 2V full scale. See Section 6.6, Reference Voltage for additional information. Lamp test. When pulled HIGH (to V+), all segments will be turned on and the display should read -1888. It may also be used as a negative supply for externally generated decimal points. See Section 7.4, TEST for additional information. See Pin 40. See Pin 40. Pins 40, 39 and 38 make up the oscillator section. For a 48kHz clock (3 readings, 39 per second), connect Pin 40 to the junction of a 180k resistor and a 50pF capacitor. The 180k resistor is tied to Pin 39 and the 50pF capacitor is tied to Pin 38. 35 36 (6) (5) VREFVREF+ 37 (4) TEST 38 39 40 (3) (2) (1) OSC3 OSC2 OSC1 (c) DS21458B-page 8 2002 Microchip Technology Inc. TC7126/A 3.0 3.1 DETAILED DESCRIPTION Dual Slope Conversion Principles A simple mathematical equation relates the input signal, reference voltage and integration time: (All Pin Designations Refer to 40-Pin PDIP.) EQUATION 3-1: VRTRI 1 TSI RC 0 VIN(t)dt = RC Where: VR = Reference voltage TSI = Signal integration time (fixed) TRI = Reference voltage integration time (variable) For a constant VIN: The conventional dual slope converter measurement cycle has two distinct phases: * Input Signal Integration * Reference Voltage Integration (De-integration) The input signal being converted is integrated for a fixed time period (TSI). Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (TRI) (see Figure 3-1). EQUATION 3-2: T V IN FIGURE 3-1: Analog Input Signal BASIC DUAL SLOPE CONVERTER Integrator + - Comparator + - The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. Noise immunity is an inherent benefit. Noise spikes are integrated or averaged to zero during integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50Hz/60Hz power line period (see Figure 3-2). Switch Driver REF Voltage Phase Control Polarity Control Control Logic Clock FIGURE 3-2: Integrator Output Display VIN VREF VIN 1.2 VREF Variable Reference Integrate Time Counter Normal Mode Rejection (dB) 30 20 Fixed Signal Integrate Time 10 In a simple dual slope converter, a complete conversion requires the integrator output to "ramp-up" and "ramp-down." 0 0.1/t 1/t Input Frequency 10/t 2002 Microchip Technology Inc. The TC7126A is a dual slope, integrating analog-todigital converter. An understanding of the dual slope conversion technique will aid in following the detailed TC7126/A operation theory. = V RT RI -----SI NORMAL MODE REJECTION OF DUAL SLOPE CONVERTER t = Measurement Period DS21458B-page 9 (c) TC7126/A 4.0 ANALOG SECTION 4.3 Reference Integrate Phase In addition to the basic integrate and de-integrate dual slope cycles discussed above, the TC7126A design incorporates an auto-zero cycle. This cycle removes buffer amplifier, integrator and comparator offset voltage error terms from the conversion. A true digital zero reading results without external adjusting potentiometers. A complete conversion consists of three phases: 1. 2. 3. Auto-Zero phase Signal Integrate phase Reference Integrate phase The third phase is reference integrate or de-integrate. VIN- is internally connected to analog common and VIN+ is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 counts. The digital reading displayed is: EQUATION 4-2: VIN 1000 V REF 4.1 Auto-Zero Phase During the auto-zero phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages. The auto-zero phase residual is typically 10V to 15V. The auto-zero cycle length is 1000 to 3000 clock periods. 5.0 DIGITAL SECTION 4.2 Signal Integrate Phase The auto-zero loop is entered and the internal differential inputs connect to VIN+ and VIN-. The differential input signal is integrated for a fixed time period. The TC7126/A signal integration period is 1000 clock periods or counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time period is: The TC7126A contains all the segment drivers necessary to directly drive a 3-1/2 digit LCD, including an LCD backplane driver. The backplane frequency is the external clock frequency divided by 800. For 3 conversions per second, the backplane frequency is 60Hz with a 5V nominal amplitude. When a segment driver is in phase with the backplane signal, the segment is OFF. An out of phase segment drive signal causes the segment to be ON (visible). This AC drive configuration results in negligible DC voltage across each LCD segment, ensuring long LCD life. The polarity segment driver is ON for negative analog inputs. If VIN+ and VINare reversed, this indicator reverses. On the TC7126A, when the TEST pin is pulled to V+, all segments are turned ON and the display reads -1888. During this mode, LCD segments have a constant DC voltage impressed. Note: Do not leave the display in this mode for more than several minutes. LCDs may be destroyed if operated with DC levels for extended periods. EQUATION 4-1: TSI = 4 FOSC x 1000 Where: FOSC = external clock frequency. The differential input voltage must be within the device Common mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, VIN- should be tied to analog common. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. The display font and segment drive assignment are shown in Figure 5-1. FIGURE 5-1: DISPLAY FONT AND SEGMENT ASSIGNMENT Display Font 1000's 100's 10's 1's (c) DS21458B-page 10 2002 Microchip Technology Inc. TC7126/A 5.1 System Timing 6.3 Integrating Capacitor (CINT) The oscillator frequency is divided by four prior to clocking the internal decade counters. The four-phase measurement cycle takes a total of 4000 counts (16,000 clock pulses). The 4000-count cycle is independent of input signal magnitude. Each phase of the measurement cycle has the following length: 1. Auto-Zero Phase: 1000 to 3000 counts (4000 to 12,000 clock pulses). For signals less than full scale, the auto-zero phase is assigned the unused reference integrate time period. 2. Signal Integrate: 1000 counts (4000 clock pulses). This time period is fixed. The integration period is: CINT should be selected to maximize integrator output voltage swing without causing output saturation. Due to the TC7126A's superior analog common temperature coefficient specification, analog common will normally supply the differential voltage reference. For this case, a 2V full scale integrator output swing is satisfactory. For 3 readings per second (FOSC = 48kHz), a 0.047F value is suggested. For 1 reading per second, 0.15F is recommended. If a different oscillator frequency is used, CINT must be changed in inverse proportion to maintain the nominal 2V integrator swing. An exact expression for CINT is: EQUATION 6-1: CINT = Where: FOSC = VFS = RINT = VINT = 1 (4000) F OSC VFS RINT EQUATION 5-1: TSI = 4000 1 FOSC VINT Where: FOSC is the externally set clock frequency. 3. Reference Integrate: 0 to 2000 counts (0 to 8000 clock pulses). Clock frequency at Pin 38 Full scale input voltage Integrating resistor Desired full scale integrator output swing The TC7126A is a drop-in replacement for the TC7126 and ICL7126, which offer a greatly improved internal reference temperature coefficient. No external component value changes are required to upgrade existing designs. At 3 readings per second, a 750 resistor should be placed in series with CINT. This increases accuracy by compensating for comparator delay. CINT must have low dielectric absorption to minimize rollover error. A polypropylene capacitor is recommended. 6.0 6.1 COMPONENT VALUE SELECTION Auto-Zero Capacitor (C AZ) 6.4 Integrating Resistor (RINT) The CAZ capacitor size has some influence on system noise. A 0.47F capacitor is recommended for 200mV full scale applications where 1LSB is 100V. A 0.033F capacitor is adequate for 2.0V full scale applications. A mylar type dielectric capacitor is adequate. The input buffer amplifier and integrator are designed with Class A output stages. The output stage idling current is 6A. The integrator and buffer can supply 1A drive current with negligible linearity errors. RINT is chosen to remain in the output stage linear drive region, but not so large that PC board leakage currents induce errors. For a 200mV full scale, RINT is 180k. A 2V full scale requires 1.8M. Component Value CAZ RINT CINT Note: Nominal Full Scale Voltage 200mV 0.33F 180k 0.047F 2V 0.033F 1.8M 0.047F 6.2 Reference Voltage Capacitor (CREF) The reference voltage, used to ramp the integrator output voltage back to zero during the reference integrate phase, is stored on CREF. A 0.1F capacitor is acceptable when VREF- is tied to analog common. If a large Common mode voltage exists (VREF- - analog common) and the application requires a 200mV full scale, increase CREF to 1F. Rollover error will be held to less than 0.5 count. A Mylar type dielectric capacitor is adequate. FOSC = 48kHz (3 readings per sec). 2002 Microchip Technology Inc. DS21458B-page 11 (c) TC7126/A 6.5 Oscillator Components 7.0 COSC should be 50pF; R OSC is selected from the equation: DEVICE PIN FUNCTIONAL DESCRIPTION Differential Signal Inputs VIN+ (Pin 31), VIN- (Pin 30) (Pin Numbers Refer to the 40-Pin PDIP.) EQUATION 6-2: FOSC = 0.45 RC For a 48kHz clock (3 conversions per second), R = 180k. Note that FOSC is 44 to generate the TC7126A's internal clock. The backplane drive signal is derived by dividing FOSC by 800. To achieve maximum rejection of 60Hz noise pickup, the signal integrate period should be a multiple of 60Hz. Oscillator frequencies of 24kHz, 12kHz, 80kHz, 60kHz, 40kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 20kHz, 100kHz, 66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings per second) will reject both 50Hz and 60Hz. 7.1 The TC7126A is designed with true differential inputs and accepts input signals within the input stage Common mode voltage range (VCM). Typical range is V+ - 1V to V- + 1V. Common mode voltages are removed from the system when the TC7126A operates from a battery or floating power source (isolated from measured system), and VIN- is connected to analog common (VCOM) (see Figure 7-2). In systems where Common mode voltages exist, the TC7126A's 86 dB Common mode rejection ratio minimizes error. Common mode voltages do, however, affect the integrator output level. A worst case condition exists if a large positive VCM exists in conjunction with a full scale negative differential signal. The negative signal drives the integrator output positive along with VCM (see Figure 7-1). For such applications, the integrator output swing can be reduced below the recommended 2V full scale swing. The integrator output will swing within 0.3V of V+ or V- without increased linearity error. 6.6 Reference Voltage Selection A full scale reading (2000 counts) requires the input signal be twice the reference voltage. Required Full Scale Voltage* 20mV 2V Note: VFS = 2VREF. VREF 100mV 1V FIGURE 7-1: COMMON MODE VOLTAGE REDUCES AVAILABLE INTEGRATOR SWING (VCOM VIN) CI RI - + Integrator tI VI = VCM - VIN RI CI Where: 4000 tI = Integration time = FOSC CI = Integration capacitor RI = Integration resistor VI In some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a pressure transducer output for 2000lb/in2 is 400mV. Rather than dividing the input voltage by two, the reference voltage should be set to 200mV. This permits the transducer input to be used directly. The differential reference can also be used where a digital zero reading is required when VIN is not equal to zero. This is common in temperature measuring instrumentation. A compensating offset voltage can be applied between analog common and VIN-. The transducer output is connected between VIN+ and analog common. + VIN - VCM + - Input Buffer [ [ (c) DS21458B-page 12 2002 Microchip Technology Inc. TC7126/A 7.2 Differential Reference VREF+ (Pin 36), VREF- (Pin 35) The TC7126A offers a significantly improved analog common temperature coefficient. This potential provides a very stable voltage, suitable for use as a reference. The temperature coefficient of analog common is typically 35ppm/C for the TC7126A and 80 ppm/C for the TC7126. The reference voltage can be generated anywhere within the V+ to V- power supply range. To prevent rollover type errors being induced by large Common mode voltages, CREF should be large compared to stray node capacitance. FIGURE 7-2: COMMON MODE VOLTAGE REMOVED IN BATTERY OPERATION WITH VIN = ANALOG COMMON Segment Drive LCD Measured System V+ VGND VBUFF VIN+ VIN- CAZ VINT POL BP OSC1 OSC3 OSC2 V- TC7126A ANALOG COMMON VREF- VREF+ V+ V+ V- GND Power Source + 9V 7.3 Analog Common (Pin 32) The analog common pin is set at a voltage potential approximately 3V below V+. The potential is between 2.7V and 3.35V below V+. Analog common is tied internally to an N-channel FET capable of sinking 100A. This FET will hold the common line at 3V should an external load attempt to pull the common line toward V+. Analog common source current is limited to 1A. Therefore, analog common is easily pulled to a more negative voltage (i.e., below V+ - 3V). The TC7126A connects the internal VIN+ and VINinputs to analog common during the auto-zero phase. During the reference integrate phase, VIN- is connected to analog common. If VIN- is not externally connected to analog common, a Common mode voltage exists, but is rejected by the converter's 86dB Common mode rejection ratio. In battery operation, analog common and VIN- are usually connected, removing Common mode voltage concerns. In systems where VIN- is connected to power supply ground or to a given voltage, analog common should be connected to VIN-. The analog common pin serves to set the analog section reference, or common point. The TC7126A is specifically designed to operate from a battery, or in any measurement system where input signals are not referenced (float) with respect to the TC7126A's power source. The analog common potential of V+ - 3V gives a 7V end of battery life voltage. The common potential has a 0.001%/% voltage coefficient and a 15 output impedance. With sufficiently high total supply voltage (V+ - V- > 7V), analog common is a very stable potential with excellent temperature stability (typically 35ppm/C). This potential can be used to generate the TC7126A's reference voltage. An external voltage reference will be unnecessary in most cases because of the 35ppm/C temperature coefficient. See Section 7.5, TC7126A Internal Voltage Reference discussion. 7.4 TEST (Pin 37) The TEST pin potential is 5V less than V+. TEST may be used as the negative power supply connection for external CMOS logic. The TEST pin is tied to the internally generated negative logic supply through a 500 resistor. The TEST pin load should be no more than 1mA. See Section 5.0, Digital Section for additional information on using TEST as a negative digital logic supply. If TEST is pulled HIGH (to V+), all segments plus the minus sign will be activated. DO NOT OPERATE IN THIS MODE FOR MORE THAN SEVERAL MINUTES. With TEST = V+, the LCD segments are impressed with a DC voltage which will destroy the LCD. 2002 Microchip Technology Inc. DS21458B-page 13 (c) TC7126/A 7.5 TC7126A Internal Voltage Reference 8.0 8.1 TYPICAL APPLICATIONS Liquid Crystal Display Sources The TC7126A's analog common voltage temperature stability has been significantly improved (Figure 7-3). The "A" version of the industry standard TC7126 device allows users to upgrade old systems and design new systems, without external voltage references. External R and C values do not need to be changed. Figure 7-4 shows analog common supplying the necessary voltage reference for the TC7126A. Several manufacturers supply standard LCDs to interface with the TC7126A, 3-1/2 digit analog-to-digital converter. Manufacturer Crystaloid Electronics AND Address/Phone 5282 Hudson Dr. Hudson, OH 44236 216-655-2429 720 Palomar Ave. Sunnyvale, CA 94086 408-523-8200 1800 Vernon St., Ste. 2 Roseville, CA 95678 916-783-7878 612 E. Lake St. Lake Mills, WI 53551 414-648-2361 Representative Part Numbers* C5335, H5535, T5135, SX440 FE 0801 FE 0203 LD-B709BZ LD-H7992AZ 3902, 3933, 3903 FIGURE 7-3: 200 180 ANALOG COMMON TEMP. COEFFICIENT VGI, Inc. No Maximum Specified Typical Analog Commom Temperature Coefficient (ppm/C) 160 140 120 100 80 60 40 20 Typical Maximum No Maximum Specified Typical Hamlin, Inc. Note: Contact LCD manufacturer for full product listing/ specifications. 8.2 Decimal Point and Annunciator Drive TC7126A 0 ICL7126 ICL7136 FIGURE 7-4: TC7126A INTERNAL VOLTAGE REFERENCE CONNECTION 9V + The TEST pin is connected to the internally generated digital logic supply ground through a 500 resistor. The TEST pin may be used as the negative supply for external CMOS gate segment drivers. LCD annunciators for decimal points, low battery indication, or function indication may be added, without adding an additional supply. No more than 1mA should be supplied by the TEST pin; its potential is approximately 5V below V+ (see Figure 8-1). FIGURE 8-1: 26 V1 V+ 240k DECIMAL POINT AND ANNUNCIATOR DRIVES Simple Inverter for Fixed Decimal Point or Display Annunciator V+ V+ TC7126A VREF+ 36 VREF VREF35 10k 4049 TC7126A BP 21 TEST 37 GND To LCD Decimal Point To Backplane ANALOG 32 COMMON SET VREF = 1/2 VREF V+ Multiple Decimal Point or Annunciator Driver V+ BP TC7126A To LCD Decimal Point To LCD Decimal Point TEST 4030 GND (c) DS21458B-page 14 2002 Microchip Technology Inc. TC7126/A 8.3 Flat Package EQUATION 8-1: Displayed (Reading) = RUNKNOWN x 1000 RSTANDARD The TC7126 is available in an epoxy 64-pin formed lead package. A test socket for the TC7126ACBQ device is available: Part Number: Manufacturer: Distribution: IC 51-42 Yamaichi Nepenthe Distribution 2471 East Bayshore, Ste. 520 Palo Alto, CA 94043 (650) 856-9332 The display will over range for RUNKNOWN 2 x RSTANDARD (see Figure 8-2). FIGURE 8-2: 8.4 Ratiometric Resistance Measurements RSTANDARD LOW PARTS COUNT RATIOMETRIC RESISTANCE MEASUREMENT VREF+ V+ VREFVIN+ LCD The TC7126A's true differential input and differential reference make ratiometric reading possible. In a ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. No accurately defined reference voltage is needed. The unknown resistance is put in series with a known standard and a current passed through the pair. The voltage developed across the unknown is applied to the input and the voltage across the known resistor is applied to the reference input. If the unknown equals the standard, the display will read 1000. The displayed reading can be determined from the following expression: RUNKNOWN TC7126A VINANALOG COMMON FIGURE 8-3: 3-1/2 DIGIT TRUE RMS AC DMM 9V 200mV VIN 9M C1 2V 1N4148 1M 0.02F 10M + 1F 1 2 3 4 AD636 14 13 12 11 10 9 8 2.2 F 1M 10% 10k 240k + 26 V+ V27 29 1 TC7126A 36 35 VREF+ VREF- 900k C2 20V 47k 1 10% 6.8F 5 + 6 7 28 90k 200V 20k 10% 0.01 F 30 26 32 ANALOG COMMON 31 V IN+ VOUT+ VBP 40 38 39 10k C1 = 3pF to 10pF, Variable C2 = 132pF, Variable Segment Drive COM LCD 2002 Microchip Technology Inc. DS21458B-page 15 (c) TC7126/A FIGURE 8-4: 9V INTEGRATED CIRCUIT TEMPERATURE SENSOR 2 V+ VOUT ADJ REF02 TEMP 3 6 5 Constant 5V V+ 51k R4 NC 51k R5 2- 8 1 1/2 LM358 3 + 4 50k R2 VREF+ TC7126A VREFVIN+ VIN- Temperature Dependent Output VOUT = 1.86V @ +25C GND 4 50k R1 COMMON V- FIGURE 8-5: TEMPERATURE SENSOR + 9V FIGURE 8-6: POSITIVE TEMPERATURE COEFFICIENT RESISTOR TEMPERATURE SENSOR + 9V 160k 300k 300k V+ VINV5.6k 1N4148 R1 20k 160k V+ VINV- 1N4148 Sensor R2 50k R1 50k VIN+ TC7126A VREF+ VREFCOMMON 0.7%/C PTC R3 R2 20k TC7126A VIN+ VREF+ VREFCOMMON (c) DS21458B-page 16 2002 Microchip Technology Inc. TC7126/A 9.0 9.1 PACKAGING INFORMATION Package Marking Information Package marking data not available at this time. 9.2 Taping Form Component Taping Orientation for 44-Pin PLCC Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PLCC 32 mm 24 mm 500 13 in Note: Drawing does not represent total number of pins. Component Taping Orientation for 44-Pin PQFP Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PQFP 24 mm 16 mm 500 13 in Note: Drawing does not represent total number of pins. 2002 Microchip Technology Inc. DS21458B-page 17 (c) TC7126/A 9.3 Package Dimensions 40-Pin PDIP (Wide) PIN 1 .555 (14.10) .530 (13.46) 2.065 (52.45) 2.027 (51.49) .610 (15.49) .590 (14.99) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .040 (1.02) .020 (0.51) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .022 (0.56) .015 (0.38) 3 MIN. .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) Dimensions: inches (mm) 44-Pin PLCC PIN 1 .050 (1.27) TYP. .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51) .021 (0.53) .013 (0.33) .630 (16.00) .591 (15.00) .032 (0.81) .026 (0.66) .656 (16.66) .650 (16.51) .695 (17.65) .685 (17.40) .180 (4.57) .165 (4.19) .020 (0.51) MIN. .120 (3.05) .090 (2.29) Dimensions: inches (mm) (c) DS21458B-page 18 2002 Microchip Technology Inc. TC7126/A 9.3 Package Dimensions (Continued) 44-Pin PQFP .009 (0.23) .005 (0.13) 7 MAX. PIN 1 .018 (0.45) .012 (0.30) .041 (1.03) .026 (0.65) .398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65) .031 (0.80) TYP. .398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65) .010 (0.25) TYP. .083 (2.10) .075 (1.90) .096 (2.45) MAX. Dimensions: inches (mm) 2002 Microchip Technology Inc. DS21458B-page 19 (c) TC7126/A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART CODE TC7126X X XXX A or blank* R (reversed pins) or blank (CPL pkg only) * "A" parts have an improved reference TC Package Code (see Device Selection Table) SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. (c) DS21458B-page 20 2002 Microchip Technology Inc. TC7126/A Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. 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Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/01/02 (c) DS21458B-page 22 2002 Microchip Technology Inc. *B85412SD* |
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